Yuan PU (蒲渊)

Ph.D. Student Department of Computer Science and Engineering
The Chinese University of Hong Kong
Supervisor: Prof. Bei YU
Email:pyxch11081210@gmail.com

Biography

I am a second-year Ph.D. Student at the Department of Computer Science and Engineering, the Chinese University of Hong Kong (CUHK), supervised by Prof. Bei YU since 2023 Fall. Prior to that, I obtained my B.Sc. degree in Computer Science from The Chinese University of Hong Kong in 2022.

Research Interest

AI/LLM in EDA
AI for Science
Combinatorial Algorithms in EDA

Publication

Conference papers

[C10] Baohui Xie, Xinrui Zhu, Zhiyuan Lu, Yuan Pu, Tongkai Wu, Xiaofeng Zou, Bei Yu, Tinghuan Chen, “DSPlacer: DSP Placement for FPGA-based CNN accelerator”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 22–25, 2025.
[C9] Haoyuan Wu, Haisheng Zheng, Yuan Pu, Bei Yu, “Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment”, International Conference on Learning Representations (ICLR), Singapore, Apr. 24–28, 2025.
[C8] Yuan Pu, Fangzhou Liu, Zhuolun He, Keren Zhu, Rongliang Fu, Ziyi Wang, Tsung-Yi Ho, Bei Yu, “HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning”, ACM International Symposium on Physical Design (ISPD), Austin, Mar. 16–19, 2025. (Best Paper Award Nomination)
[C7] Yuan Pu, Zhuolun He, Tairu Qiu, Haoyuan Wu, Bei Yu, “Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), New Jersey, Oct. 27–31, 2024. (Best Paper Award Nomination)
[C6] Hongduo Liu, Peng Xu, Yuan Pu, Lihao Yin, Hui-Ling Zhen, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu, “NeuroSelect: Learning to Select Clauses in SAT Solvers”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 23–27, 2024.
[C5] Yuan Pu, Fangzhou Liu, Yu Zhang, Zhuolun He, Kai-Yuan Chao, Yibo Lin, and Bei Yu. “Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs,” ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 23–27, 2024.
[C4] Yu Zhang, Yuan Pu, Fangzhou Liu, Peiyu Liao, Kaiyuan Chao, Keren Zhu, Yibo Lin, Bei Yu, “Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells”, ACM International Symposium on Physical Design (ISPD), Taipei, Mar. 12–15, 2024.
[C3] Yuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu, “IncreMacro: Incremental Macro Placement Refinement”, ACM International Symposium on Physical Design (ISPD), Taipei, Mar. 12–15, 2024. (Best Paper Award Nomination)
[C2] Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu, “FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler (Extended Abstract)”, International Joint Conference on Artificial Intelligence (IJCAI), Macau, Aug. 19–25, 2023.
[C1] Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu, “Realistic Sign-off Timing Prediction via Multimodal Fusion”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jul. 09–13, 2023

Journal papers

[J8] Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu, “PRO-TIME: Pre-routing Optimization-aware Timing Prediction via Multimodal Learning”, accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
[J7] Yuan Pu, Zhuolun He, Yuqi Jiang, Tairu Qiu, Haoyuan Wu, Qi Sun, Cheng Zhuo, Bei Yu, “Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA”, accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
[J6] Zhuolun He, Yuan Pu, Haoyuan Wu, Tairu Qiu, Bei Yu, “Large Language Models for EDA: Future or Mirage?”, accepted by ACM Transactions on Design Automation of Electronic Systems (TODAES).
[J5] Jiahao Xu, Zhuolun He, Shuo Yin, Yuan Pu, Wenjian Yu, Bei Yu, “EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling”, accepted by ACM Transactions on Design Automation of Electronic Systems (TODAES).
[J4] Yuan Pu, Tinghuan Chen, Zhuolun He, Jiajun Qin, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu, “IncreMacro: Incremental Macro Placement Refinement”, accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
[J3] Zhuolun He, Yuan Pu, Haoyuan Wu, Yuhan Qin, Tairu Qiu, Bei Yu, “Large Language Models for EDA: From Assistants to Agents”, accepted by Foundations and Trends in Electronic Design Automation.
[J2] Ziyi Wang, Wenqian Zhao, Yuan Pu, Lei Chen, Wilson Wang Kit Thong, Weihua Sheng, Tsung-Yi Ho, Bei Yu, “ParSGCN: Bridging the Gap Between Emulation Partitioning and Scheduling”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.
[J1] Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu, “FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 42, no. 07, pp. 2317–2330, 2023.

Education

Ph.D., Department of Computer Science and Engineering, The Chinese University of Hong Kong (CUHK), Aug/2023 - Now
B.Sc., Department of Computer Science and Engineering, The Chinese University of Hong Kong (CUHK), Aug/2018 - Jun/2022

Experiences

ChatEDA Technology Foshan, China

Intern, Jan. 2024 - Now

Shanghai AI lab Shanghai, China

Intern, Oct. 2022 - Jul. 2023

CUHK Hong Kong, China

Research assistant, Jun. 2022 - Jun. 2023
Supervised by Prof. Bei YU

SmartMore Hong Kong, China

Intern, Jan. 2022 - Jul. 2022